1. Field of the Invention
This invention relates to a multi-chip packaging (MCP) substrate having non-sticking test structure, and more particularly to a multi-chip packaging substrate having non-sticking test structure of xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) type.
2. Description of Related Art
In the light of the trend of xe2x80x9cLight, Thin, Short, and Smallxe2x80x9d of the electronic product, in only as short as a decade, the chip packaging technology of semiconductor has developed from the xe2x80x9cInsertion Mountxe2x80x9d type in 1980s to the xe2x80x9cChip Scale Package (CSP) technology of today. The xe2x80x9cInsertion Mountxe2x80x9d type of chip packaging simply mounts the chip on the Print Circuit Board (PCB) while the xe2x80x9cChip Scale Package (CSP) technology has high density of electronic devices and is also in three dimensions instead of the two-dimensional package that were made previously.
During the course of the development of the packaging technology, the BGA package has imperceptibly become the main stream of packaging type nowadays, particularly, the BGA package having Multi-Chip Module (MCM) has been the principal research and development target of large corporations in the field of IC packaging.
FIG. 1 is a schematic top view of a substrate for the ball grid array package having single chip according to the prior art. FIG. 1A is a schematic cross-sectional view illustrates the fabricating process that a chip and a substrate are performing wire bonding. As shown in FIG. 1 and FIG. 1A, a molding gate 110, which is used as an injecting gate of molding compound for injection molding during the encapsulating process, is employed as a non-sticking test spot 110. Besides, the molding gate, which is provided on the substrate, is also used to facilitate separating the molded BGA type package from the substrate after molding. The chip pad 102 is electrically connected to the non-sticking test spot 10 through a conductive trace 104, and a plurality of bonding fingers is disposed at the periphery of the chip pad 102.
After a chip 114 is bonded on the chip pad 102, a wire bonding process is performed to make the chip 114 and the bonding finger 112 of the BGA type packaging substrate 100 electrically connected. The bond wire 116 acts as electrical connection between the chip 112 and BGA packaging substrate 100. In general, during the course of wire bonding, after the bond wire 116 forming a first bond on the bonding pad 118 of the chip 114, a xe2x80x9cnon-sticking testxe2x80x9d is performed. The purpose of the test is to check if the electrical connection between the first bond and the bonding pad 118 of the chip 114 is in good condition, in other words, to make sure whether the phenomena of xe2x80x9cMissing Wirexe2x80x9d or xe2x80x9cLift Bondxe2x80x9d occurs between them.
A non-sticking test spot 110 is formed in a periphery zone 108 outside the chip-packaging zone, and an electroconductive trace 104 is formed on the BGA packaging substrate 100. For the non-sticking test, usually an electroconductive trace 104 is used to make the chip 114 and the non-sticking test spot 110 form an electrical connection through the chip pad 102. Thereafter, the chip 114 is electrified, and the non-sticking test spot 110 is probed to check the existence of electric current. Whether or not there is electric current existed at the non-sticking test spot 110 is used to judge the condition of electrical connection between the first bond formed on the bonding pad 118 of the chip 114 and the bonding pad 118 itself. Normally, the non-sticking test spot 110 is the molding gate, and the method to judge the condition of the electrical connection between first bond and the bonding pad 118 was disclosed in the U.S. Pat. No. 5,712,570.
FIG. 2 is a schematic top view of a substrate for the ball grid array package having multi-chip according to the prior art. As shown in FIG. 2, a multiple of the chip pads 202a, 202b, 202c, and 202d are electrically connected to the molding gate 210 respectively through the conductive traces 204, 204c, 204b and 204a. After all the chips are bonded to the chip pads 202a, 202b, 202c, and 202d of a BGA packaging substrate 200, similarly, a wire bonding process is performed to make the chips and the BGA packaging substrate 200 electrically connected.
The bond wire is used for electrically connecting the chip to the BGA packaging substrate 200. During the course of wire bonding, after the bond wire forming a first bond on the bonding pads of the chip respectively, a xe2x80x9cnon-sticking testxe2x80x9d is performed. Again, the purpose of the test is to check if the electrical connection between the first bond and the bonding pads of the chip is in good condition.
The foregoing method for BGA package having single chip uses the molding gate 210 in the periphery zone 208 outside the chip-packaging zone 206 as the sole non-sticking test spot of the non-sticking test. However, if one still employs the foregoing method for BGA package having single chip, then these chip pads 202a, 202b, 202c, and 202d must share a non-sticking test spot. Therefore, a multiple of conductive traces 204a, 204b, and 204c must be used to form electrical connection among the chip pads 202a, 202b, 202c, and 202d. And then another conductive trace 204 is used to electrically connect these chip pads to the molding gate 210 of the non-sticking test spot. These conductive traces 204a, 204b, and 204c, also called ground traces, will make the ground signals of the multi-chip in the multi-chip package connect together.
However, when the chips are under operation, the ground signals will be interfered one another that will cause problems for the chips if the circuit is not designed for a single ground signal. This is because that when the chips are under operation, the chips in the package are connected by the grounded conductive traces. Therefore, the circuit design of the non-sticking test spot of the multi-chip package""s non-sticking test using only the xe2x80x9cmolding gatexe2x80x9d can only be applied in the circuit design for a single ground signal.
The above-mentioned problems can be resolved by removing or cutting off these grounded conductive traces. However, since these grounded conductive traces are designed to form in a chip-packaging zone having narrow and small space, the work of removing and cutting off the traces are not an easy one to perform.
Additionally, as far as the multi-chip packaging (MCP) is concerned, the circuit design having only a single non-sticking test spot has to use a multiple of conductive traces in order to connect the ground signals together among the chips. Consequently, a xe2x80x9cwiring-around designxe2x80x9d is necessary which will make the circuit design in a very narrow and small space even more complicated and difficult
According to the above-mentioned statements, the conventional multi-chip packaging substrate has the disadvantage of using only a circuit design for a single non-sticking test spot that results in the inability to be applied in a multi-chip packaging having two or more than two different ground signals. Besides, the disadvantage also the circuit design even more complicated and difficult. Therefore, in the light of the foregoing disadvantages, the present invention provides a multi-chip packaging substrate to resolve the above-mentioned problems.
The present invention provides a multi-chip packaging substrate having a non-sticking test structure. The multi-chip packaging substrate comprises a packaging substrate, a plurality of non-sticking test spots, a molding gate, a plurality of first conductive traces, and a plurality of second conductive traces. The packaging substrate has a chip-packaging zone and a periphery zone wherein the chip-packaging zone has a plurality of chip pads. The plurality of non-sticking test spots is disposed in the periphery zone of the packaging substrate. The molding gate is also disposed in the periphery zone of the packaging substrate. The plurality of first conductive traces is disposed on the packaging substrate for making each of the chip pads electrically connect to each of the adjacent non-sticking test spot respectively. And the plurality of second conductive traces is disposed on the periphery of the packaging substrate for making each of the non-sticking test spot electrically connect to one another.
The present invention is to form a plurality of non-sticking test spots in the periphery zone outside the chip-packaging zone of a multi-chip packaging substrate. Each of these non-sticking test spots is electrically connected to an adjacent one of a plurality of chip pads respectively in the chip packaging zone through a plurality of conductive traces while there are no electrical connection one another among the chip pads.
The present invention makes each of the chip pads electrically connected to each of the non-sticking test spots through a conductive trace while there are no electrical connection one another among the chip pads. In spite of the fact that these non-sticking test spots will become electrically connected through the conductive trace which make each of the chips commonly grounded one another during the non-sticking test. However, after the packaging process is completed, these non-sticking test spots will all be removed. Therefore, each of the chips will not be commonly grounded one another any more. Consequently, the ground signals of each of the chips under operation will not be interfered one another that will further improve the devices"" reliability under operation.
Besides, the present invention does not need to connect each of the chips by the conductive trace, thereby, there is no need to employ the xe2x80x9cwiring-around designxe2x80x9d. As far as the very narrow and small packaging space of a multi-chip package is concerned, the present invention provides a simple and flexible circuit design.